Monday, August 15, 2011

Cu Integrated with Low-k Dielectrics: The Future Is NOW

Speed no longer depends on feature size, but on interconnect distance.
To allow the continuation of Moore's Law, IC manufacturers have increased the power of semiconductor devices by decreasing feature size. However, the limiting factor the industry is facing when reaching 0.13 µm technology nodes and beyond is an increase in signal delays at the interconnect level. Smaller feature sizes mean increased density, closer proximity of circuit interconnects and bigger line-to-line capacitance, which results in an even greater signal delay. Interconnect delays increase with the square of the reduction in feature size whereas gate delays generally decrease linearly with the same reduction in feature size. When reaching the 0.18 µm node, the speed performance of a device no longer depends on its feature size but on interconnect distance.
The conventional approach to compensate for this increased delay is to add more layers of metal, but this increases production costs and generates more heat in the device, affecting its performance and reliability. To avoid these cost and performance problems and still allow the continuation of Moore's Law, the industry is migrating to copper instead of conventional aluminum as the interconnect metal. Copper has much greater conductivity than aluminum and is less susceptible to electro-migration, allowing the copper lines to be thinner under current load.
However, to significantly increase speed performance in next generation devices, copper must be integrated with ultra-low-k dielectrics (k< 2.5). The transition to copper alone only improves speed performance by 30% but when silicon oxide (k= 4) is replaced with ultra-low-k dielectrics an increase in speed performance can be as high as 266%. Today's low-k dielectrics strategy is a gradual migration from oxide (k= 4) to fluorinated oxide (k= 3.5) to low-k dielectrics (k< 3) and finally to ultra-low-k materials below k= 2. And since each generation of dielectric materials has different mechanical properties and characteristics, device manufacturers need to develop CMP and other related processes for each generation of dielectric material. Such a multi-step strategy is, however, very costly and high risk because of the uncertainty for the success of device manufacturability, tool and process extendibility, manufacturing yield and device reliability. An alternative to the migration strategy described above is to leap directly to ultra-low-k dielectrics below 2.2. The risk and cost of migrating to tighter design rules will be substantially lower because of the elimination of expensive development cycles for each generation of dielectric and its associated process integration challenges. Ultra-low-k dielectrics are generally porous and their k value can easily be changed by increasing the porosity without changing the actual material and process tool. However, the ultra low k dielectrics used in copper structures have insufficient adhesion and mechanical strength to survive the stress placed on them by a conventional CMP process.

Fig 1a Rupture in the line Fig 1b Delamination of low k Fig 1c Stress free polishing
The physical limitations of CMP especially for 0.13 µm manufacturing nodes and beyond have created a challenge for the IC industry in adopting low k material and aggressive design rules. Developing a viable solution for these processes integrated with ultra low k dielectrics without compromising device performance reliability yield and overall cost of ownership has become most challenging. Due to the mechanical force applied in conventional CMP, copper lines are moved back and forth during the polishing process. This results in critical damage to the interconnect structures Figure 1a, delamination of the ultra low k dielectric Figure 1b, and eventually yield loss in the current 0.13 µm process technologies making it highly unextendable for future technology nodes.
A stress free polishing SFP technology developed by ACM Research is the semiconductor industry's first to provide a copper low k integration capability that enables the leap from conventional oxide to ultra low k dielectrics. The new process called Ultra SFPTM induces no mechanical stress on the wafer because it is a non contact electric current controlled process Demonstrated results Figure 1c confirm the absence of mechanical damage to copper interconnect lines or to the ultra low k dielectrics. Since mechanical strength is no longer an issue for the low k dielectric process integration these results allow for an accelerated implementation time frame of ultra low k dielectrics into copper interconnect structures. Migration to smaller design rules is made easier without the impact of the costly development of each generation of low k dielectric slurries pads qualifications characterizations of the process and related integration issues
The Process The concept was developed to remove copper by using a stress free process based on electropolishing as in reverse electro plating In the past experiments with electropolishing were abandoned because of unsuccessful results on the wafer. When the technique was applied to polishing copper on a wafer difficulties were encountered in controlling thickness uniformity from the center of the wafer to its edge. The profile of a copper film polished with the conventional electropolishing method showed that the thickness of the copper film at the edge of the wafer was close to zero. However the center of the wafer showed over 3000 Å thickness forcing the polishing process to stop otherwise no current would pass through the center of the wafer to the edge where the electrode is located. These problems were resolved by applying the new patented technology employing localized control ensuring a highly uniform removal rate from the center to the edge of the wafer independent of wafer size. The SFP system uses localized current and voltage control dividing the wafer into zones that are polished in sequence starting at the center. Think of it as the circular ripple of a raindrop when it hits the water.

Figure 2 The Ultra SFP can achieve a throughput of 30 wafers per hour using multiple stacked chambers accessed by dual robot end effectors
The precise control of power supply allows the SFP process to control the removal of copper at the atomic layer level meaning its copper removal rate is  proportional to the current density. In addition, ACM has demonstrated on customer wafers a thickness removal within wafer nonuniformity of 0.8 to 1.2% (1 sigma) and corresponding thickness removal wafer-to-wafer nonuniformity of 0.59% (1 sigma).
Because only the copper is removed during the Ultra SFP process, no dielectric loss or erosion has been observed using the technique. This will significantly improve the global planarity of the interconnect layer as the number of stacked interconnect layers increases, particularly for most logic devices such as CPUs or ASICs, which may have up to ten layers in the future.
The stand-alone, single-wafer processing system can achieve a throughput of 30 wafers per hour using multiple stacked chambers accessed by dual robot end-effectors (Figure 2). The use of multiple stacked modules, three polishing and three cleaning modules including bevel and backside cleaning, reduces the system foot-print dramatically to 6 x 10 x 8 ft, about half the size of a typical CMP tool, enhancing the system's COO. The stress free polishing system also achieves a significantly lower cost-per-wafer than CMP tools because it does not use slurries, pads, and pad conditioning. In addition, capital productivity is higher due to elimination of process-induced defects such as erosion, delamination, dielectric loss, lithography de-focusing and scratches.

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