Sunday, June 7, 2009

DFEB Methodology Validated for 65-nm Test Chip


Design-for-e-beam (DFEB) methodology has been validated for low-volume, 65-nm system-on-chip applications, according to a consortium of companies created to develop and promote DFFEB.

The EE Times reported on Tuesday, May 26 that “D2S Inc., e-Shuttle Inc. and Fujitsu Microelectronics Ltd. collaborated on a test chip with a final estimated shot count that was more than 10X lower than can be achieved with conventional e-beam direct-write technologies, according to the eBeam Initiative.The test chip meet all the required performance, power and area goals, according to the group. “

A paper on the new technology will be available after May 29

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